CGL Meeting Agenda

Wednesday, July 15th, 1998

Location:
DC 1304
Time:
1:30
Chair:
Clara Tsang
:-)
Member List

1. Adoption of the Agenda - additions or deletions

2. Coffee Hour

Coffee hour last week:
Thank you, Blair and Marryat
Coffee hour this week:
Mark Riddell
Coffee hour next week:
Snoop Poggy Pog (Patrick Gilhuly)

3. Next meeting

Date:
Wednesday, July 22, 1998
Location:
DC 1304
Time:
1:30
Chair:
Teresa Yeung :-)
Technical presentation:
Liddy Olds :-)

4. Forthcoming

Chairs:
  1. Shalini Aggarwal (July 29th)
    2. :-(
  2. Berj Bannayan (August 5th)
    3. :-(
  3. Richard Bartels (August 12nd)
    4. :-)
Tech Presenters:
  1. Mark Riddell (July 29th) :-)
  2. Ian Stewart (August 5th) :-)
  3. Teresa Yeung (August 12) :-)

5. Technical Presentation

Presenter:
Dan Milgram :-)
Title:
Xhier (Somewhat) Demystified
Abstract:
The vast majority of software available campus-wide is maintained and distribute through "xhier"- a locally developed system designed for this express purpose. I will explain how it works, how it fits in within the realm of system administration in general, and provide criticism.

6. General Discussion Items

7. Action List

8. Director's Meeting

9. Seminars

************************************************************************ 
 Speaker:  Prof. David L. Dill, Stanford University
 Date: Wednesday, July 15th
 Time: 3:00pm.
 Place: DC1302

 Title:  Towards Practical Formal Verification of Microprocessors
 
 Abstract:
 
 Full formal verification of a commercial microprocessor design could
 be considered a "grand challenge" problem for formal verification
 researchers.  However, many of the grand challenges that have been
 proposed (such as weather prediction) don't double in complexity every
 couple of years!
 
 In this talk, I will discuss some of ideas we have had over the last
 few years for new ideas to formally verifying microprocessor designs,
 based on symbolic simulation and analysis, and some of the problems
 on the way to a practical solution to this problem.

************************************************************************ 

Thursday, July 16, 1998 

Ph.D. Defence
``Process Spaces and Formal Verification of Asynchronous Circuits''
Radu Negulescu, CS Graduate Student, Univ. of Waterloo
1:30 p.m.; DC 1304

************************************************************************ 

COMPUTER SCIENCE SEMINAR 

                    -Friday, July 17, 1998

Robert Berks, graduate student, Dept. Comp. Sci., Univ.
Waterloo, will speak on ``Tree-based FIFOs''.

TIME:                10:00-11:00 a.m.

ROOM:                MC 5158

ABSTRACT
FIFOs  are a common part of many circuits and are often
designed  as a simple linear array of cells.  Designers
striving  for  high speed and low power consumption may
need  to  consider  alternative architectures, however.
An   asynchronous   tree-based   architecture   is  one
architecture  that  has been proposed to reduce latency
and  power  consumption  by reducing the number of data
movements  in  a  FIFO.   On  the other hand tree-based
architectures  have  been  criticised  for  being  more
difficult to design and lay out.

This  talk discusses the benefits, and disadvantages of
asynchronous  tree-based  architectures  and  contrasts
them  with  linear  pipelines.   By using a new timing-
analysis  technique  one  can show that one can improve
the  layout  and  area  of a tree without affecting the
throughput.   Thus  we  can  have  all the power-saving
benefits of a tree without significant disadvantages.


 
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10. Lab Deep-cleanup