CGL Meeting Agenda

Wednesday, November 6th, 1996

Valid HTML
Location:
DC 2303 (Lab)
Time:
11:30 AM
Chair:
Richard Bartels

1. Adoption of the Agenda - additions or deletions

2. Coffee Hour

Coffee hour this week:
To be determined
Coffee hour next week:
To be determined

3. Next meeting

Date:
November 13th, 1996
Location:
DC 2303 (Lab)
Time:
11:30 AM
Chair:
John Beatty
Technical presentation:
Wilkin Chau

4. Forthcoming

Chairs:
  1. Balasingham Balakumaran
  2. Bill Cowan
  3. Itai Danan
Tech Presenters:
  1. Richard Bartels
  2. John Beatty
  3. Balasingham Balakumaran

5. Technical Presentation

Presenter:
Navid Sadikali
Title:
Unknown
Abstract:
Yet to come.

6. General Discussion Items

  1. Empty

7. Action List

  1. Navid Sadikali and Richard Bartels:
    UofT visit in April

8. Director's Meeting

9. Seminars

                   PC Hardware and Troubleshooting One
                                    by
                               Chris Rovers

 Ever  wonder how your PC  works?  What  goes on inside  that box?   Do you
know what to do if it breaks?
 This is  the first half of a set of talks  on Troubleshooting PC Hardware.
This one  assumes you know  almost nothing about  the internals of  your PC.
I'll be discussing memory, cards, bus types and other internals.  There will
also be a question session.

                       Wednesday, November 6, 1996
                                 4:30 pm
                                 Room TBA

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DEPARTMENT OF COMPUTER SCIENCE AND PURE MATHEMATICS
UNIVERSITY OF WATERLOO
SEMINAR ACTIVITIES

JOINT NUMBER THEORY/COMPUTER SCIENCE THEORY SEMINAR

                    -Thursday, November 7, 1996

Dinesh Thakur, Department of Mathematics, University of
Arizona,  will speak on ``Automata and transcendence in
finite characteristic''.

TIME:                4:30-5:30 p.m.

ROOM:                MC 5045

ABSTRACT

After   describing   the  automata-based  criterion  of
Christol   for  algebraicity,  we  will  describe  some
applications  to  the  theory  of  elliptic  curves and
Drinfeld modules.

=============================================================
DEPARTMENT OF COMPUTER SCIENCE
UNIVERSITY OF WATERLOO
SEMINAR ACTIVITIES

VLSI SEMINAR

                    -Wednesday, November 6, 1996

Prof.  T.  Luba, Institute of Telecommunications of the
Warsaw  University  of  Technology  (WUT) will speak on
``Multiple-Valued Decomposition and its Applications in
Logic Synthesis and Information Systems Analysis''.

TIME:               3:30-4;30 p.m.

ROOM:               DC 3574

ABSTRACT

Decomposition  is a fundamental problem in modern logic
synthesis.  Its goal is to break a logic circuit into a
set   of   smaller   interacting  components.  Such  an
implementation  is desirable for a number of reasons. A
decomposed  circuit  usually leads to a smaller silicon
area and shorter signal delays.

Recent  motivation  for  studying decomposition methods
comes  from the field of programmable multi-block logic
devices.  Such  technologies  are characterized by I/O-
limited  or gate-limited blocks of logic into which the
circuit  must  be mapped. In such a case implementation
is impossible without decomposition.

A  strong stimulus for developing decomposition methods
and  tools comes also from data compression problems in
machine learning, pattern recognition and in many other
areas of AI.

In  this talk we concentrate on a generalization of the
decomposition   methodology  to  improve  the  existing
FPGA-based synthesis algorithms, as well as to make the
methodology   applicable   to   multiple-valued   logic
synthesis.

ABOUT THE SPEAKER

Tadeusz Luba is the head of a research group within the
Institute  of  Telecommunications  at  WUT. His current
research  interests  are  in the area of multiple-level
logic    optimization   including   decomposition   and
factorization,     two-level     and     multiple-level
minimization,  microprogrammable  control  systems, and
analysis   of   information  systems  with  respect  to
decision  table  optimization.  Prof. Luba has authored
numerous publications in the area of Logic Synthesis.

10. Lab Cleanup (until 12:30 or 5 minutes)