Unknown at time of preparation. ===============================The presenter - or reasonable facsimile - will gas on for some time on some topic or other.
Splines and Graphics Seminar
Computer Graphics Lab
University of Waterloo
Date: Wednesday, June 21, 1995
Time: 4:30 PM
Place: William G. Davies Computer Research Centre, Room 2102
SCIENTIFIC COMPUTATION SEMINAR
-Thursday, June 22, 1995
Peter Forsyth, Dept. Comp. Sci., University of Waterloo
"Full Newton Solution of the Euler
Equations: An Object Oriented Approach".
TIME: 1:30-2:30 p.m.
ROOM: DC 3301
ABSTRACT
Full Newton nonlinear iteration using a Jacobian based
on a high order discretization is compared with a
widely used technique which uses a first order
Jacobian. The linearized equations are solved using a
level based block incomplete LU factorization with
CGSTAB acceleration. Numerical tests are carried out
using various standard airfoil shapes, at transonic and
supersonic conditions. The full Newton, high order
Jacobian technique is more robust and efficient than
the usual approach.
The entire code was developed in C++. The PCG matrix
solver implementation in C++ is compared with a Fortran
implementation of the same algorithm. Provided that
operator overloading is not used, the C++
implementation is only about 10% slower than a Fortran
implementation.
ICR Distinguished Visitor Series
Institute for Computer Research
Presents a Lecture on
"Trends in VLSI Memory Technology"
by
ICR Distinguished Visitor
Dr. Kiyoo Itoh
Central Research Laboratory
Hitachi Ltd.
Tokyo, Japan
Wednesday, June 28, 1995: 2:30 p.m.
Davis Centre, Room 1302
Abstract:
Trends in VLSI memory technology are reviewed with emphasis on
DRAM technology. First, current topics of 1-Gb DRAM, 4-Mb SRAM
and 32 Mb flash memory are described after memory chip trends are
reviewed. Then, DRAM technology is discussed in terms of the
following three key design issues in the sub-micron era.
(i) High density technology: structural advancement and size
reduction of memory cell, on-chip voltage down converter for
realizing power-supply standardization, and multi-data-bit chip
configuration for ease of use are addressed.
(ii) Low power/low voltage design: circuit advancements, which
have produced a power reduction equivalent to 2 to 3 orders of
magnitude over the last decade, are explained from the viewpoint
of reductions of charging capacitance, operating voltage and
static current; sub threshold current issue, which is the key to
ultra-low voltage operation, is also discussed.
(iii) High performance architecture: high-speed column modes,
synchronous DRAM, Rambus DRAM, and embedded DRAM are exemplified
as recent important movements.
Biography
Kiyoo Itoh is the Senior Chief Scientist of Hitachi Ltd.'s Cen-
tral Research Laboratory. He received BS and PhD degrees in
Electrical Engineering from Tohoku University, Japan, in 1963 and
1976.
From 1963 to 1971, Dr. Itoh was a member of the technical staff
of Hitachi Central Research Laboratory, Kokubunji, Tokyo, Japan,
where he worked on design on magnetic core and thin film
memories. In 1972 he became the lead designer of the first pro-
totype for eight generations of Hitachi DRAMs ranging from 4Kb to
64Mb. His designs have formed the basis for each generation of
product designs. In 1991 he assumed his present position as the
Senior Chief Scientist of Hitachi Central Research Laboratory.
In 1994 he as a Visiting MacKay Lecturer at the Department of
Electrical Engineering and Computer Science at the University of
California at Berkeley. His current research interests include
studies of low power/low voltage LSIs.
As a result of his 23-year DRAM career, Dr. Itoh holds over 120
patents in both Japan and the US. The most important one is the
folded data (or bit)-line circuit for DRAMs, invented in 1974.
This circuit has become the universal approach in DRAMs because
of its noise suppression and Vcc/2 sensing ability. Other impor-
tant patents that he holds include: the Video-RAM (invented in
1975); the Vcc/2 precharging (1977); the multi-divided data-line
(1981); the pipe-line memory (1981); the on-chip voltage-down
converter (1981); and static column mode (1981). His other major
contributions have been in the development of high-density DRAMs.
He and his team have led the development of DRAM technology
through about 100 papers and presentations. Dr. Itoh is also the
author of "VLSI Memory Design" (Baifukan, in Japanese), published
in 1994, and the recipient of numerous awards for his research.