The University of Waterloo 200 University Avenue Waterloo, Ontario The Institute for Computer Research (ICR) Presents a Colloquium on Uncheatable Benchmarks by: Dr. Jin-yi Cai of: Department of Computer Science SUNY Buffalo Buffalo, New York Date: Wednesday, April 12, 1995 Time: 3:30 pm. Place: William G. Davis Computer Research Centre, Room 1302 Abstract: Benchmarks have been used to test everything from the speed of a processor, to the accuracy of computations, to the capacity of a memory system. The computing community relies heavily on the use of benchmarks to assess how well a given hardware or software system operates. The recent fiasco involving the Pentium chips is an excellent reminder that while certain computations may seem elementary, adequate testing using good benchmarks is indispens- able. Up until now, the study of the art of designing a good benchmark has focused on making the benchmark ``realistic'' in predicting how well it will perform for the intended applications; the issue of making benchmark results trustworthy has been relegated to ``trusted'' or third party agents, and little attention has been paid to the question of making benchmarks themselves ``uncheat- able''. We wish to study the problem of how one can make benchmarks resistant to tampering and hence more trustworthy. We propose a framework based on modern cryptography and complexity theory. Concrete schemes are proposed for different benchmarks: speed of the processor, memory capacity, sorting, etc. They are ``un- cheatable'', if certain complexity theory assumptions are true based on the hardness of factoring and discrete logarithm. We also present a scheme for matrix multiplication which depends on the numerical instability of certain floating point arithmet- ic. If time permits we will present a new scheme which could have captured the errors in the Pentium chip. Part of this talk will be based on joint work with R. Lipton, R. Sedgewick and A. Yao, and also joint work with my students S. Ar and A. Nerurkar. Supported by NSF grant CCR9319393 and CCR9057486, and a Sloan fellowship. Everyone is welcome. Refreshments served.
DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF WATERLOO SEMINAR ACTIVITIES FORMAL SPECIFICATION AND VERIFICATION SEMINAR -Monday, April 17, 1995 Graham Birtwistle, Computer Science, University of Calgary, will speak on "Specifying and Verifying AMULET in CCS". TIME: 11:00-12:00 noon ROOM: DC 1304 ABSTRACT Asynchronous hardware design is attracting renewed research and industrial interest because of its compositional properties and potential for low power consumption (much of today's hardware is battery driven and asynchronous circuits only do work when there is work to do). AMULET is an (already working) asynchronous version of the ARM micro designed by Steve Furber's team at Manchester University. ARM is now a standard TI cell, used by IBM to control disks, and in the Apple Newton. Its outstanding characteristic is perhaps its very low power consumption (132 MIPS per watt). The medium term expectation is that AMULET will fare even better. The talk will present work in progress at Calgary on specifying and verifying the major subsystems of AMULET (address interface, register bank, execution pipeline, data interface) in CCS and modal mu respectively and at the RTL. CCS does not handle data well, so we are concentrating our efforts on the way blocks (a)synchronise. Once the major subsystems are specified they are tested for deadlock and livelock, bus contention, etc. using modal mu. So far we have completed work on the address interface, and are well on the way towards specifying the other major subsystems, and a more abstract specification which will be useful when we come to consider embedded systems centered on AMULET. The work is being carried out with Ms Ying Liu (PhD student) and with the full cooperation of the Manchester AMULET team.