CGL Meeting Agenda
Wednesday, March 22, 1995
- Location:
- DC 1304
- Time:
- 1:30 PM
- Chair:
- Randall Reid
1. Adoption of the agenda - additions/deletions thereto.
2. Coffee Hour and Next Meeting:
- Coffee hour this week:
- Jay Steele
- Coffee hour next week:
- ???
- Next Meeting
-
- Time:
- March 29, 1995
- Location:
- DC 1304
- Chair:
- Stephen Mereu
- Tech Presentation:
- Sandra Loop
- Forthcoming: (list next 4 and trades)
-
- Chairs:
- Haroon Sheikh
- Jay Steele
- Riston Tapp
- Greg Veres
- Tech presentations:
- Michael McCool
- Stephen Mereu
- Andrew Park
- Glenn Paulley
3. Technical Presentation:
- Presenter:
- Robert Kroeger
- Title:
- Pathology and Treatment of the ACL deficient knee
- Abstract:
- Rob will be sharing with us (in graphic details ?) his experiences over
his summer vacation
4. General Discussion Items:
-
5. Action List (remember to update AL_active)
6. Directors Meeting:
7. Seminar(s):
DEPARTMENT OF COMPUTER SCIENCE
UNIVERSITY OF WATERLOO
SEMINAR ACTIVITIES
DATABASE SEMINAR
-Friday, March 24, 1995
Dexter Bradshaw, graduate student, Dept. Comp. Sci.,
Univ. Waterloo, will speak on "Composite Multidatabase
Concurrency Control and Recovery".
TIME: 1:30-2:30 p.m.
ROOM: DC 1304
ABSTRACT
A multidatabase management system is an abstraction
that provides a single view of data in multiple,
possibly heterogeneous, disparate database systems
dispersed on a communications network. Most current
research view a multidatabase system as a centralized
monolithic server isolated from other multidatabase
environments. This view defeats the multidatabase
abstraction and limits the flexibility and
configurability of multidatabase environments. In this
talk, multidatabase environments are viewed as a
composite multidatabase system: sets of cooperating,
distinct, distributed, and possibly heterogeneous
multidatabase servers. Each server controls a data
domain, or multidatabase cell. Servers may dynamically
delegate data access request from one cell to another
making some cells appear like simple component database
systems for some requests and like multidatabase
environments for others.
During multidatabase composition, data accesses are
made through multiple concurrent interleaving
transactions. Global transactions are assumed to be
globally serializable and to possess the ACID
properties. Unfortunately, most global concurrency
algorithms for simple multidatabase systems do not
scale to composite environments. This talk identifies
the keys issues to this problem and some solutions are
introduced. These solutions augment global concurrency
control algorithms for simple multidatabase systems to
Constrain transaction orders across cells. However,
these constraints are susceptible to global restarts
spanning multiple cells. A mechanism for containing
rollbacks within the boundary of a single cell is also
introduced to mitigate the effects of frequent global
restarts.
Biography --------- Dexter Bradshaw is a Ph.D.
candidate in the Department of Computer Science,
University of Waterloo. He holds a B.Sc. degree in
Mathematics and Computer Science from the University of
the West Indies (U.W.I. - UWeee), and an M.Math. degree
in Computer Science at the University of Waterloo. He
is currently involved in the multidatabase research
project at Waterloo and his current research interests
include distributed transaction management, distributed
object management systems, distributed embedded real-
time systems, and real-time database systems.
DEPARTMENT OF COMPUTER SCIENCE
UNIVERSITY OF WATERLOO
SEMINAR ACTIVITIES
SOFTWARE SYSTEMS SEMINAR
-Friday, March 24, 1995
Xinxin Wang, Ph.D. candidate, Dept. Comp. Sci., Univ.
Waterloo, will speak on "Handling Tabular Formatting
Problem".
TIME: 1:00-2:00 p.m.
ROOM: DC 1331
ABSTRACT
The goal of our research is to create a generic tabular
model to support different stages of tabular
composition, including logical structure design,
topological arrangement, style specification, and
formatting. The formatting process decides the physical
dimensions of a table based on user-defined
constraints. The factors that complicate the formatting
process include:
1 The approaches to handle line breaking: fixed line
breaking or automatic line breaking.
2. The size constraints on the columns and rows.
3 The objective function for evaluating the quality
of a tabular layout, such as minimal perimeter,
area or white space.
Automatic line breaking is the crucial factor that
makes this problem an NP-complete problem.
In this talk I will review previous work, then give a
formal definition of tabular formatting problem and
prove its NP-completeness. I also present an algorithm
that can solve the problem in polynomial time for most
common tables. This algorithm allows automatic line
breaking and the size constraints expressed in linear
inequalities. We have disregarded the object functions
in order to achieve higher computational efficiency.
DEPARTMENT OF COMPUTER SCIENCE
UNIVERSITY OF WATERLOO
SEMINAR ACTIVITIES
COMPUTER SCIENCE SEMINAR
-Monday, March 27, 1995
Allan Silburt, Manager, H.W System Modelling, Bell
Northern Research, will speak on "Behavioural Modelling
in ASIC Design and System Verification."
NOTE: Because of some job opportunities at BNR,
graduating students (preferably with Master's degree)
with experience and interest in hardware modelling and
verification using hardware description languages are
encouraged to attend.
TIME: 3:30-4:30 p.m.
ROOM: DC 1302
ABSTRACT
The advent of gate level synthesis technology has
brought Hardware Description Languages such as Verilog
and VHDL into common usage in ASIC design. However,
the full potential of these languages as vehicles to
drive the specification and verification process has
not been fully exploited. In this talk, a process will
be described which involves the use of a behavioural
model as an essential component of an individual ASIC
specification, as well as serving an essential role in
ASIC and board verification. In deploying this process
on a large ASIC intensive system (8 ASICs totaling
about 500K gates of complexity) over 200 issues of
which 32 were of highest priority were made visible
early in the implementation. In addition, the ASIC
design cycle was reduced due to the concurrent RTL
coding and top level verification that was enabled by
following this flow. The presentation will include
metrics on design effort for these models, their
distinction from synthesizable RTL models, simulation
speed, bugs found during the various stages of
verification and overall impact on the design interval.
8. Lab Cleanup (till 2:30pm or 5 minutes, whichever is longer)